tag:blogger.com,1999:blog-1575376285321445036.comments2011-05-08T03:52:27.627+05:30Art of verificationSaravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.comBlogger8125tag:blogger.com,1999:blog-1575376285321445036.post-5924436740100035732011-05-08T03:52:27.627+05:302011-05-08T03:52:27.627+05:30Yes, the method you have suggested will work.But i...Yes, the method you have suggested will work.But it is procedural randomization,it is not through the constraint solver randomization. You can not have a real type to be rand variable in system verilog.Saravananhttps://www.blogger.com/profile/11967368690794767974noreply@blogger.comtag:blogger.com,1999:blog-1575376285321445036.post-44897383380735002962011-05-08T03:46:30.663+05:302011-05-08T03:46:30.663+05:30you can make it uni-directional by using void term...you can make it uni-directional by using void termination or using solve before. See this post for details<br /><br />http://art-of-verification.blogspot.com/2010/12/uni-directional-bi-directional.htmlSaravananhttps://www.blogger.com/profile/11967368690794767974noreply@blogger.comtag:blogger.com,1999:blog-1575376285321445036.post-6426202904801776522011-05-03T22:53:09.790+05:302011-05-03T22:53:09.790+05:30By nature all the constraints are Bi-directional.
...By nature all the constraints are Bi-directional.<br />How can you change the constraints from Bi-directional to uni-directional. Can you explain with example.Vishnu Prasanthhttps://www.blogger.com/profile/09847963413954027879noreply@blogger.comtag:blogger.com,1999:blog-1575376285321445036.post-37270927048453504732011-05-03T22:49:42.916+05:302011-05-03T22:49:42.916+05:30But there is a way to generate random real numbers...But there is a way to generate random real numbers in Systemverilog.<br /><br />reg sgn; <br /> reg [10:0] exp; <br /> reg [51:0] man; <br /> real r_num; <br /><br /> initial <br /> begin <br /> repeat(5) <br /> begin <br /> sgn = $random; <br /> exp = $random; <br /> man = $random; <br /> r_num = $bitstoreal({sgn,exp,man}); <br /> $display("r_num = %e",r_num); <br /> end <br /> endVishnu Prasanthhttps://www.blogger.com/profile/09847963413954027879noreply@blogger.comtag:blogger.com,1999:blog-1575376285321445036.post-61257714276943507402011-01-16T08:48:52.092+05:302011-01-16T08:48:52.092+05:30Formal verification is more about getting hands on...Formal verification is more about getting hands on experience verifying design with the formal tools like 0-in from mentor graphics & IFV from cadence.Knowledge of SVA and PSL assertions will be very handy skill for formal verification. Try getting access to this tools through your university and experiment some projects of medium complexity with the formal tool. User manual of the tool will be a good starting point to know about formal verification.Saravananhttps://www.blogger.com/profile/11967368690794767974noreply@blogger.comtag:blogger.com,1999:blog-1575376285321445036.post-64786066875220012862011-01-16T04:01:16.090+05:302011-01-16T04:01:16.090+05:30Mr. Saravanan.
I doing my grad studies at CSUS. I ...Mr. Saravanan.<br />I doing my grad studies at CSUS. I want to learn formal verification. I have knowledge of System Verilog (VMM) and good grip in SVA as well. What would be a good approach, where can I find th necessary material.<br /><br />Thank you.Anonymoushttps://www.blogger.com/profile/14678266779461462947noreply@blogger.comtag:blogger.com,1999:blog-1575376285321445036.post-14581316358783428882010-03-18T02:22:11.467+05:302010-03-18T02:22:11.467+05:30If UVM is going to be third new methodology withou...If UVM is going to be third new methodology without any resemblence with OVM or VMM, It will be not be beneficial for either OVM or VMM user to migrate to UVM. Having backward comptibility with any one of the methodology in this case OVM will defenitly be beneficial. As an VMM/RVM user I definitly want to see some of the VMM features being added to this methdology but always open to other better ways of solving verification problems. It would be interesting to see the views of other VMM/RVM users.Saravananhttps://www.blogger.com/profile/11967368690794767974noreply@blogger.comtag:blogger.com,1999:blog-1575376285321445036.post-24723129526899302512010-03-18T00:18:56.683+05:302010-03-18T00:18:56.683+05:30Those of us involved in the OVM are working hard t...Those of us involved in the OVM are working hard to ensure that Accellera does not *not* create a third methodology, but rather standardizes the OVM as the UVM. This provides backwards compability for OVM usrs as well as a standard interoperability link (also defined by Accellera) between the UVM and VMM useers.Unknownhttps://www.blogger.com/profile/00942657781810145851noreply@blogger.com