tag:blogger.com,1999:blog-15753762853214450362024-02-07T23:13:04.120+05:30Art of verificationA blog to share my knowledge in ASIC design verification with respect to verification environment architecture, verification methodology, verification languages, protocols & EDA tool evaluations.Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.comBlogger81125tag:blogger.com,1999:blog-1575376285321445036.post-14556341022080032712014-11-25T10:51:00.000+05:302014-11-25T10:51:47.262+05:30Interface class in system verilog !!!<br />
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<span style="letter-spacing: 0.0px;">System verilog 2012 has introduced interface class. Interface class is nothing but class with pure virtual methods declaration. The class which implements the interface class should implement the pure virtual methods. Interface class can extend from another interface class but it cannot extend from virtual class or regular class. Regular class can implement multiple interface class and also extend from regular class. Interface class enables better code reusability and also enables multiple inheritance.</span></div>
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<span style="letter-spacing: 0.0px;">Example </span></div>
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<span style="letter-spacing: 0.0px;">interface class A;</span></div>
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<span style="letter-spacing: 0.0px;"> pure virtual function int get();</span></div>
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<span style="letter-spacing: 0.0px;">endclass</span></div>
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<span style="letter-spacing: 0.0px;">interface class B;</span></div>
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<span style="letter-spacing: 0.0px;"> pure virtual function void put()</span></div>
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<span style="letter-spacing: 0.0px;">endclass</span></div>
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<span style="letter-spacing: 0.0px;">class C implements A , B;</span></div>
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<span style="letter-spacing: 0.0px;"> virtual function int get();</span></div>
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<span style="letter-spacing: 0.0px;"> $display(“ Get \n”);</span></div>
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<span style="letter-spacing: 0.0px;"> endfunction</span></div>
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<span style="letter-spacing: 0.0px;"> virtual function void put();</span></div>
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<span style="letter-spacing: 0.0px;"> $display(“ Put \n”);</span></div>
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<span style="letter-spacing: 0.0px;"> endfunction</span></div>
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<span style="letter-spacing: 0.0px;">endclass </span></div>
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Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-38079651525900624442014-09-28T20:51:00.001+05:302014-09-28T20:51:06.010+05:30p_sequencer usage in UVM !!! <br />
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<span style="letter-spacing: 0px;">UVM sequences generally do not have access to the TLM ports In that case the TLM ports and other features available in the sequencer can be accessed from the sequence using p_sequencer reference. This feature is very useful in a layering scenario when higher level sequence is layered into the lower level sequence.</span></div>
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Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-43780807859550755322014-08-31T11:50:00.001+05:302014-08-31T11:50:27.361+05:30Barrier in UVM !!!<br />
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<span style="letter-spacing: 0px;">uvm_barrier class is used for multi process synchronization mechanism. set of processes can be allowed to wait using the wait_for() method until desired number of process reach a synchronization point. set_threshhold() method specifies how many process must be waiting on the barrier synchronization point before all the processes may proceed. reset() method resets the barrier waiter count to zero , after reset all the process should wait for the threshold again.</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-83445279036165501192014-07-26T18:52:00.000+05:302014-10-02T16:16:45.081+05:30uvm_event and uvm_event_pool !!! <br />
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<span style="letter-spacing: 0px;">Synchronization in a multithreaded environment in system verilog is done using event’s. In UVM uvm_event and uvm_event_pool can be used for synchronization of multiple threads or components. Simple example of uvm event is as follows.</span></div>
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<span style="letter-spacing: 0px;">uvm_event_pool event_pool_s=uvm_uvm_event_pool::get_global_pool()</span></div>
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<span style="letter-spacing: 0px;">uvm_event event_s=event_pool_s.get(event_s);</span></div>
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<span style="letter-spacing: 0px;">fork</span></div>
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<span style="letter-spacing: 0px;">begin</span></div>
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<span style="letter-spacing: 0px;"> ........</span></div>
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<span style="letter-spacing: 0px;"> event_s.trigger();</span></div>
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<span style="letter-spacing: 0px;">end</span></div>
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<span style="letter-spacing: 0px;">begin</span></div>
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<span style="letter-spacing: 0px;"> .......</span></div>
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<span style="letter-spacing: 0px;"> event_s.wait_ptrigger();</span></div>
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<span style="letter-spacing: 0px;">end</span></div>
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<span style="letter-spacing: 0px;">join</span></div>
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Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-581733040390769732014-05-25T17:30:00.002+05:302014-05-25T17:30:27.161+05:30Parameterized class in system verilog !!!<br />
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<span style="letter-spacing: 0.0px;">Verification component reuse is one of the basic requirement when building verification components.Parameterized class play a very important role in making a code generic. With parameterized class in system verilog data types , size of bit vectors can be declared generic in the class , different variations of the class can be created by varying the parameter value.</span></div>
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<span style="letter-spacing: 0.0px;">Example of a parameterized class</span></div>
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<span style="letter-spacing: 0.0px;">class data # ( type t=int , int size=8 )</span></div>
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<span style="letter-spacing: 0.0px;"> t a ;</span></div>
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<span style="letter-spacing: 0.0px;"> bit [ size-1 : 0] b ;</span></div>
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<span style="letter-spacing: 0.0px;">endclass</span></div>
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<span style="letter-spacing: 0.0px;">data # ( shortint , 16 ) halfword_data;</span></div>
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<span style="letter-spacing: 0.0px;">data # ( longint , 32) word_data;</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-91271761669833319612014-04-20T17:00:00.001+05:302014-04-20T17:00:41.886+05:30Pure virtual functions and tasks in system verilog !!!<br />
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<span style="letter-spacing: 0.0px;">Virtual function/tasks defined in the base class may or may not be overridden in the derived class and the base class can have an implementation of the virtual function/task. sometime the definition of virtual functions/task in base class may not have any clarity on what need to be implemented these virtual functions/task must be overridden in the derived class and just a declaration is need in the base class. In this scenario virtual function / task is declared as pure. Declaring virtual method pure means no implementation for the function/task is required in the base class and the derived class must override the virtual function/task. </span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-86139585582309158452014-03-30T12:40:00.000+05:302014-03-30T12:40:50.245+05:30OOP method to access variables of the derived class !!!<br />
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<span style="letter-spacing: 0.0px;">We typically use virtual set_() and get_() methods to access the variables added in the extended class from the base class. class handles are created using the base class and type and instance factory overrides are used to replace the class handles respectively. Any reference to the derived class variable from base class is done using virtual set_() and get_() methods which are just empty methods in the base class. At runtime the derived class virtual methods are linked and variables are written or read using set and get methods after a type or instance override.</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-62729826813652642782014-02-21T12:10:00.000+05:302014-02-21T12:10:07.350+05:30Mirrors in UVM RAL !!! <br />
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<span style="letter-spacing: 0.0px;">RAL mirrors are shadow location of the DUT registers that are updated when RAL read or write methods are accessed from the test bench , RAL mirror give the user test bench access to the register values for synchronizing test bench events without reading the DUT register.</span><span style="font-family: Times; letter-spacing: 0px;"> </span><span style="letter-spacing: 0.0px;">If the DUT internally modifies the content of any field or register through its normal operations (e.g., by setting a status bit or incrementing an accounting counter), the mirrored value becomes outdated. Memory are not mirrored in UVM RAL.</span><span style="letter-spacing: 0px;">RAL mirror value can be set using mirror() method , Mirror value can be updated to the DUT using update() method. At any point of time mirror value can be got using the get() method. set() method can be used to set the mirror value to DUT , the value actually written only when update() method is called.</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-434411538264667072014-01-13T20:06:00.001+05:302014-01-13T20:06:17.505+05:30Creating directed scenario in UVM !!!<br />
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<span style="font-family: Times, Times New Roman, serif; letter-spacing: 0px;">Recommended method for closing coverage is to have test to run with multiple seeds , but many times certain scenarios can never be covered by the randomness and we require a directed test case. The way to write a directed test in UVM is as follows.</span><br />
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<li><span style="font-family: Times, 'Times New Roman', serif; letter-spacing: 0px;">Disable the regular sequence from executing on the sequencer by setting count as 0 in the directed test case.</span></li>
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<span style="font-family: Times, Times New Roman, serif;"><span style="letter-spacing: 0px;"> </span><span style="letter-spacing: 0.0px;">set_config_int("*.sequencer", "count", 0);</span></span></div>
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<li><span style="font-family: Times, Times New Roman, serif; letter-spacing: 0px;">randomize the sequence in the directed way and execute the sequence </span><span style="font-family: Times, 'Times New Roman', serif; letter-spacing: 0px;">on the sequencer using execute_item() method.</span></li>
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<span style="font-family: Times, Times New Roman, serif; letter-spacing: 0px;"> *.sequencer.execute_item(item);</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-34517139072689072512013-12-22T23:19:00.000+05:302013-12-22T23:27:43.223+05:30Collecting Coverage using white box assertion and functional coverage !!! <br />
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<span style="letter-spacing: 0.0px;">One of the essential requirement for verification closure is to close functional coverage , coverage measured should accurately measure if the event has occurred in the DUT and the DUT has responded as expected for the event , this requirement can typically be covered using white box assertion and having cover property on the assertion. Using assertion coverage instead of functional coverage is a tradeoff that has to be taken , assertion coverage removes the need for coding coverage monitor but the assertion coverage constructs are not as powerful as the the functional coverage construct in terms of covering cross coverage , having excludes in cross coverage. Most of the cross in assertion coverage need to be done manually. Best strategy one can use is to partition the coverage model between white box coverage assertion and functional coverage on the IO bus to get the best out of both the coverage approach. </span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-73878725279630273802013-11-03T08:45:00.000+05:302013-11-03T08:45:19.044+05:30TLM 2.0 Sockets in UVM !!!<br />
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<span style="letter-spacing: 0.0px;">Normally the connection between two processes is through port and export , but with TLM 2.0 we have sockets which provide asynchronous pipelined bi directional connectivity between components. Socket has both a export and port packaged together. A socket can be initiator socket or target socket. Data flows in the forward direction from the initiator socket to target socket , there is also a backward path between Target socket to initiator socket. TLM connectivity between components can be easily encapsulated using sockets.</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-44904962231783385402013-10-13T15:31:00.000+05:302013-10-13T15:31:00.437+05:30Phases in UVM !!! <br />
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<span style="letter-spacing: 0.0px;">UVM component have different phases like build() , connect() , end_of_elaboration() , start_of_simulation(), run() , extract() , check() & report(). Except run() all other phases are virtual functions , run() phase is a virtual task.</span></div>
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<span style="letter-spacing: 0.0px;">phases operate in a particular sequence as follows build -> connect --> end_of_elaboration --> start_of_simulation --> run --> extract --> check --> report. All the phases except build() phase is bottom up , build phase is top down. In UVM we have provision to add custom phase.</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-65974037290869163082013-09-29T10:31:00.000+05:302013-09-29T10:31:29.569+05:30TLM process communication using TLM FIFO !!!<br />
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<span style="letter-spacing: 0.0px;">With normal TLM ports put will result in the consumers ability to process the transaction right away , TLM FIFO component in UVM is used to buffer transactions so that producer and consumer are independent of each other. TLM FIFO has methods like put() , get() and peek() to access transaction from the TLM FIFO. peek() method gets the transaction without removing transaction from the TLM FIFO. Some of the applications of TLM FIFO is buffering transactions for score boarding. </span><br />
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Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-83565383514442599092013-08-15T12:21:00.000+05:302013-08-19T07:56:11.445+05:30Build in command line options in UVM !!! <br />
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<span style="letter-spacing: 0.0px;">here are some of the useful build in command line options in UVM.</span></div>
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<span style="letter-spacing: 0.0px;">instance specific factory override : +uvm_set_inst_override</span></div>
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<span style="letter-spacing: 0.0px;">type specific factory override : +uvm_set_type_override</span></div>
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<span style="letter-spacing: 0.0px;">integer configuration : +uvm_set_config_int</span></div>
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<span style="letter-spacing: 0.0px;">string configuration : +uvm_set_config_string</span></div>
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<span style="letter-spacing: 0.0px;">Timeout : +UVM_TIMEOUT</span></div>
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<span style="letter-spacing: 0.0px;">Max quit count : +UVM_MAX_QUIT_COUNT</span></div>
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<span style="letter-spacing: 0.0px;">Objection trace : +UVM_OBJECTION_TRACE</span></div>
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<span style="letter-spacing: 0.0px;">These command line options helps in quick debug and test writing. </span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-11916359187709262482013-07-13T08:05:00.000+05:302013-07-13T08:05:56.978+05:30System verilog assertion coverage !!! <br />
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<span style="letter-spacing: 0.0px;">Functional coverage collection with passive monitor is the method recommended by methodology to collect coverage. There is alternative ways to collect coverage in system verilog using assertion coverage. This feature is very useful if you want to collect coverage on some important DUT events , using assertion coverage has its own advantages and disadvantages.</span></div>
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<span style="letter-spacing: 0.0px;">Advantages of assertion coverage </span></div>
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<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">Coverage monitors are not required to collect required coverage event and then trigger a cover group.</span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">Coverage is collected using assertions and using cover property , binding the assertion to the module or instance is required to collect coverage from the DUT. </span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">Implementing and collecting assertion coverage is faster compared to writing functional coverage for DUT events.</span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;">Assertion coverage is perfect fit for collecting coverage on important DUT events.</li>
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<span style="letter-spacing: 0.0px;">Disadvantages of assertion coverage</span></div>
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<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">Assertions coverage if not coded appropriately takes considerable amount of simulation time.</span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">Debugging assertion failures is slightly complex than debugging coverage events in a passive monitor.</span></li>
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Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-17853234277063385612013-06-01T08:08:00.001+05:302013-06-01T08:08:52.419+05:30Sequence library in UVM !!!<br />
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<span style="letter-spacing: 0.0px;">Sequences can be grouped using uvm sequence library , sequences can be registered to sequence library using the macro `uvm_add_to_seq_lib(). When the sequence library is started it randomly selects and executes the sequence depending on the selection mode. Selection modes can be any of the following</span></div>
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<span style="letter-spacing: 0.0px;">UVM_SEQ_LIB_RAND -- Random selection of sequence </span></div>
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<span style="letter-spacing: 0.0px;">UVM_SEQ_LIB_RANDC -- Random selection without repeating the sequences</span></div>
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<span style="letter-spacing: 0.0px;">UVM_SEQ_LIB_ITEM -- Execute a single sequence item</span></div>
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<span style="letter-spacing: 0.0px;">UVM_SEQ_LIB_USER -- user selects sequences using select_sequence() method</span></div>
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<span style="letter-spacing: 0.0px;">Selection mode of the sequence library is set using uvm_config_db().</span></div>
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sequence library can be used to create system level scenario using random sequences.</div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-18196181901096739912013-05-02T16:59:00.000+05:302013-05-02T16:59:55.886+05:30Interrupt handling using grab() and ungrab() sequencer in UVM !!! <br />
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<span style="letter-spacing: 0.0px;">One of the basic functionality on the processor interface of a verification environment is to service interrupts along with register read / write operations. Servicing the interrupt requires stoping the ongoing register access sequence and executing the ISR sequence . This can be achieved using grab() method on the sequencer on an interrupt to stop the register read/write sequence and execute the interrupt sequence. ungrab() method should be used to return the sequencer control back to the register read/write sequence.</span><br />
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Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-15676650363735113592013-04-06T07:45:00.002+05:302013-04-06T10:01:26.943+05:30Generic Payload in UVM !!!<br />
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<span style="letter-spacing: 0.0px;">Generic payload is the default transport vehicle for TLM2 blocking and non blocking transport interface. Generic payload is a transaction class derived from uvm_sequence_item which enables it to be generated in sequences and transported to drivers through sequencers. Generic payload can be used for any memory mapped bus based system. Generic payload has property like m_address , m_command, m_byte_enables etc. Generic payload class has access methods for each of the property which is virtual enabling it to be used in the class that extends generic payload class.</span></div>
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<span style="letter-spacing: 0.0px;">It would be good idea to explore the generic payload transaction class before writing your own transaction class for memory mapped bus interface.</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-85949772028583753052013-03-10T01:19:00.000+05:302013-03-10T01:19:44.821+05:30Base class library specific to product on top of RVM/VMM/OVM/UVM !!!<br />
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<span style="letter-spacing: 0.0px;">RVM/VMM/OVM/UVM provides rich set of features that can be used to develop a sophisticated test bench. Extending your Driven/monitor/scoreboard/sequence directly from the methodology may not be an ideal solution with respect to product specific requirement. The ideal way is have a set of base class extending from the methodology class which adds specific requirement which will be product line specific. Having company/product specific base class helps in better reuse and isolates the users from the changes introduced due to new releases in the methodology. When ever specific base class is changed it can be qualified with the supported version of tool,methodology and VIP. This approach also helps to incrementally move towards the latest releases of the methodology ensuring current development effort is not stalled.</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-63889930712309993242013-02-02T20:17:00.000+05:302013-02-02T20:17:31.645+05:30Layering sequences in UVM !!! <br />
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<span style="letter-spacing: 0.0px;">We come across different types of layering requirement for different protocols. Basic ones are as follows.</span></div>
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<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">One to one mapping -- One higher level protocol frame is mapped to the payload of one lower level protocol frame.</span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">One to many mapping -- One higher level protocol frame is mapped to the payload of many lower level protocol frames.</span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">Many to one mapping -- Many higher level protocol frames are mapped to the payload of single lower level protocol frame.</span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">Many to many mapping -- Many higher level protocol frames are mapped to the payload of many lower level protocol frames. </span></li>
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<span style="letter-spacing: 0.0px;">What ever be the layering scenario , the basic principle to generate a layering transaction is to randomize the higher level sequence and use byte_pack to convert it to a byte stream and package the bytes in the lower level sequence.</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-45357384137805160462013-01-01T11:17:00.000+05:302013-01-01T11:17:21.411+05:30System verilog 2012 features !!!<br />
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<span style="letter-spacing: 0.0px;">I recently came across a paper presented at DVcon 2012 which summarized the proposed features of system verilog 2012 standard. The feature that first grabbed my attention was multiple inheritance support in system verilog similar to Java. This feature will ease the test bench development effort in future. The current methodology based on system verilog will potentially leverage this feature when it is available. Other feature which is also a good addition is the soft constraints which allow the constraints to be overridden without creating a conflict , currently we have to turn of the conflicting constraints using constraint mode to override a constraint. another interesting addition is the unique constraint to generate unique values across a list of variable or array elements , currently most of the users use custom logic or algorithm to generate unique values.</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-89659601727261947242012-12-01T08:08:00.001+05:302012-12-01T08:08:13.560+05:30Callback in UVM !!! <div style="font-family: Helvetica; font-size: 12px;">
<span style="letter-spacing: 0.0px;">Callbacks are empty virtual methods that are embedded in the user components at strategic points to allow the user to make customization which allows better reuse.</span></div>
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<span style="letter-spacing: 0.0px;">In UVM this can be achieved in two ways. </span></div>
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<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">Simply add empty virtual methods in the component say in a driver and invoke the virtual methods at appropriate locations , test writer or the user extends the driver class implements the virtual methods and uses set instance override to accomplish the functionality.</span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;">Create a class which extends form uvm_callback class and it implements the virtual methods. Use `uvm_do_callbacks() to place the virtual methods at strategic points in the component say a driver. Now the test writer or user extends the callback class and implements the virtual methods and registers or associate the extended callback class with the instance of the component say the driver using add to accomplish the functionality.</span></li>
</ol>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-4688948703406103452012-11-03T08:46:00.001+05:302012-11-03T08:50:56.181+05:30Adding user defined phase using uvm_phase !!!<br />
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<span style="letter-spacing: 0.0px;">In addition to the predefined phases available in uvm , the user has the option to add his own phase to a component. This is typically done by extending the uvm_phase class the constructor needs to call super.new which has three arguments </span></div>
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<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;"> name of the phase task or function</span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;"> top down or bottom up phase</span></li>
<li style="font-family: Helvetica; font-size: 12px; margin: 0px;"><span style="letter-spacing: 0.0px;"> task or function</span></li>
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<span style="letter-spacing: 0.0px;">The call_task or call_func and get_type_name need to be implemented to complete the addition of new phase.</span></div>
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<span style="letter-spacing: 0.0px;">Example</span></div>
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<span style="letter-spacing: 0.0px;">class custom_phase extends uvm_phase;</span></div>
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<span style="letter-spacing: 0.0px;"> function new();</span></div>
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<span style="letter-spacing: 0.0px;"> super.new(“custom”,1,1);</span></div>
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<span style="letter-spacing: 0.0px;"> endfunction</span></div>
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<span style="letter-spacing: 0.0px;"> task call_task ( uvm_component parent);</span></div>
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<span style="letter-spacing: 0.0px;"> </span></div>
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<span style="letter-spacing: 0.0px;"> my_comp_type comp;</span></div>
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<span style="letter-spacing: 0.0px;"> if ( $cast(comp,parent) )</span></div>
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<span style="letter-spacing: 0.0px;"> comp.custom_phase();</span></div>
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<span style="letter-spacing: 0.0px;"> </span></div>
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<span style="letter-spacing: 0.0px;"> endtask</span></div>
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<span style="letter-spacing: 0.0px;"> virtual function string get_type_name();</span></div>
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<span style="letter-spacing: 0.0px;"> return “custom”;</span></div>
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<span style="letter-spacing: 0.0px;"> endfunction</span></div>
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<span style="letter-spacing: 0.0px;">endclass</span></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-47849746125389308802012-10-02T17:00:00.000+05:302012-10-04T06:47:47.047+05:30Usage of uvm_resource_db & uvm_config_db !!!<div class="MsoNormal">
Both uvm_config_db and uvm_resource_db share the same underlying
database to store and retrieve information. Infact you can write a
value to the database using uvm_config_db ::set() method and retrieve the information
using uvm_resource_db::read_by_name().
The recommended method is to use uvm_config_db when hierarchical based access is required. When you want to share object and access it from different
location without using the hierarchy you can use uvm_resource_db.<o:p></o:p></div>
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You can set a resource to the resource db using the
uvm_resource_db::set() method<o:p></o:p></div>
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Example<o:p></o:p></div>
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uvm_resource_db# (int)::set("enable","*",1,this);<o:p></o:p></div>
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To retrieve the information from the resource db you can use
uvm_resource_db::read_by_name() method<o:p></o:p></div>
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Example<o:p></o:p></div>
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Bit success;<o:p></o:p></div>
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Success=uvm_resource_db#(int)::read_by_name("enable",get_full_name(),value,this);<o:p></o:p></div>
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If(success==1’b0)<br />
`uvm_error("ERROR","cannot locate
the resource ");<o:p></o:p></div>
<br />Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0tag:blogger.com,1999:blog-1575376285321445036.post-5404616783694821862012-09-02T08:58:00.001+05:302012-09-02T08:58:08.145+05:30Accessing components bottom up using set_config_* and get_config_* in UVM !!!<br />
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One of the requirements in verification is to access
variable bottom up in the hierarchy this
can be done in UVM using set_config_* and get_config_*methods. In bottom up access
you need to use hierarchical reference like
uvm_test_top.set_config_* or uvm_test_top.get_config_* from the component in the lower level hierarchy
to access component in top level hierarchy. Top down access does not require the hierarchical
reference to uvm_test_top , set_config_* and get_config_* can be used directly. <o:p></o:p></div>
Saravananhttp://www.blogger.com/profile/11967368690794767974noreply@blogger.com0