TLM 2.0 Sockets in UVM !!!

Normally the connection between two processes is through port and export , but with TLM 2.0 we have sockets which provide asynchronous pipelined bi directional connectivity between components. Socket has both a export and port packaged together. A socket can  be initiator socket or target socket. Data flows in the forward direction from the initiator socket to target socket , there is also a backward path between Target socket to initiator socket. TLM connectivity between components can be easily encapsulated using sockets.

Phases in UVM !!!

UVM component have different phases like build() , connect() , end_of_elaboration() , start_of_simulation(), run() , extract() , check() & report().  Except run() all other phases are virtual functions , run() phase is a virtual task.

phases operate in a particular sequence  as follows build ->  connect  -->  end_of_elaboration --> start_of_simulation --> run --> extract --> check --> report. All the phases except build() phase is bottom up , build phase is top down. In UVM we have provision to add custom phase.

TLM process communication using TLM FIFO !!!

With normal TLM ports put will result in the consumers ability to process the transaction right away , TLM FIFO component in UVM is used to buffer transactions so that producer and consumer are independent of each other. TLM FIFO has methods like put() , get() and peek() to access transaction from the TLM FIFO. peek() method gets the transaction without removing transaction from the TLM FIFO. Some of the applications of TLM FIFO is buffering transactions for score boarding. 

Build in command line options in UVM !!!

here are some of the useful build in command line options in UVM.

instance specific factory override  :   +uvm_set_inst_override

type specific factory override          :   +uvm_set_type_override

integer configuration                        :   +uvm_set_config_int

string configuration                           :   +uvm_set_config_string

Timeout                                               :   +UVM_TIMEOUT

Max quit count                                   :   +UVM_MAX_QUIT_COUNT

Objection trace                                  :   +UVM_OBJECTION_TRACE

These command line options helps in quick debug and test writing. 

System verilog assertion coverage !!!

Functional coverage collection with passive monitor is the method recommended by methodology to collect coverage. There is alternative ways to collect coverage in system verilog using assertion coverage. This feature is very useful if you want to collect coverage on some important DUT events , using assertion coverage has its own advantages  and disadvantages.

Advantages of assertion coverage 

1. Coverage monitors are not required to collect required coverage event and then trigger a cover group.
2. Coverage is collected using  assertions and using cover property , binding the assertion to the module or instance is required to collect coverage from the DUT. 
3. Implementing and collecting assertion coverage is faster compared to writing functional coverage for DUT events.
4. Assertion coverage is perfect fit for collecting coverage on important DUT events.

Disadvantages of assertion coverage

1. Assertions coverage if not coded appropriately takes considerable amount of simulation time.
2. Debugging assertion failures is slightly complex than debugging coverage events in a passive monitor.

Sequence library in UVM !!!

Sequences can be grouped using  uvm sequence library ,  sequences can be registered to sequence library using the macro `uvm_add_to_seq_lib(). When the sequence library is started it randomly selects and executes the sequence depending on the selection mode. Selection modes can be any of the following

UVM_SEQ_LIB_RAND      --  Random selection of sequence 

UVM_SEQ_LIB_RANDC   --  Random selection without repeating the sequences

UVM_SEQ_LIB_ITEM       --  Execute  a single sequence item

UVM_SEQ_LIB_USER      --  user selects  sequences using select_sequence() method

Selection mode of the sequence library is set using  uvm_config_db().

sequence library can be used to create system level scenario using random sequences.

Interrupt handling using grab() and ungrab() sequencer in UVM !!!

One of the basic functionality on the processor interface of a verification environment is to service interrupts along with register read / write operations. Servicing the interrupt requires  stoping the ongoing register access sequence and executing the ISR sequence . This can be achieved  using grab()  method on the sequencer on an interrupt to stop the register read/write sequence and execute the interrupt sequence. ungrab() method should be used to return the sequencer control back to the register read/write sequence.