Saturday, October 8, 2011

Gate level simulation !!!

One of time-consuming task in functional verification life cycle is gate level simulation. Gate level simulation can be broadly broken down into

1) Gate level simulation after synthesis to check equivalence with the RTL.

2) Gate level simulation with SDF on the post routed netlist.

A common question that is asked by many fokes is why step 2 is required. The netlist before P & R is compared with the netlist after P & R using formal tools for logic equivalence. Timing after P & R is checked with STA for all possible corners and configuration. It looks like an SDF simulation on post routed netlist is redundant.

Assume now a designer by mistake has place timing exception like false path and multi cycle path, the above condition goes undetected in the STA. Dynamic functional gate level simulation with SDF on post routed netlist is counter check for STA and catches if the designer has made mistakes on placing an timing exception.

Wednesday, October 5, 2011

Code coverage !!!

Coverage closure be it functional coverage or code coverage is one of the time consuming task in functional verification life cycle. With respect to functional coverage automatic coverage closure tools are available in the market. When it comes to code coverage it is very tedious and manual process to measure and close coverage, Code coverage number (Line, condition, fsm , toggle) of 95% is unacceptable in many places. The remaining 5 % coverage holes need to be completely analyzed and closed. More perfection requires more time and resource . Generally code coverage analysis is done by verification engineers who have relatively less knowledge in design this impacts the overall efficiency of the task execution. Why is code coverage important especially when we have functional coverage ? missing test cases are captured easily by code coverage which seems to have slipped through the functional coverage plan.

It is good idea to not include the register package test for code coverage as this test would give a false pass on the register coverage. We generally expect the register to be covered using functional tests, by including register package test we will end up covering registers by just doing a read and write to all the bits which is not our intent.