p_sequencer usage in UVM !!!

UVM sequences generally do not have access to the TLM ports  In that case the TLM ports and other features available in the sequencer can be accessed from the sequence using p_sequencer reference. This feature is very useful in a layering scenario when higher level sequence is layered into the lower level sequence.

Barrier in UVM !!!

uvm_barrier class is used for multi process synchronization mechanism. set of processes can be allowed to wait using the wait_for() method until  desired number of process reach a synchronization point. set_threshhold() method specifies how many process must be waiting on the barrier synchronization point before all the processes may proceed. reset() method resets the barrier waiter count to zero , after reset all the process should wait for the threshold again.

uvm_event and uvm_event_pool !!!

Synchronization in a multithreaded environment in system verilog is done using event’s. In UVM uvm_event and uvm_event_pool can be used for synchronization of multiple threads or components. Simple example of uvm event is as follows.

uvm_event_pool  event_pool_s=uvm_uvm_event_pool::get_global_pool()

uvm_event           event_s=event_pool_s.get(event_s);

fork

begin

    ........

    event_s.trigger();

end

begin

    .......

  

   event_s.wait_ptrigger();

end

join

OOP method to access variables of the derived class !!!

We typically use virtual set_() and get_() methods to access the variables added in the extended class from the base class. class handles are created using the base class and type and instance factory overrides are used to replace the class handles respectively. Any reference to the derived class variable from base class is done using virtual set_() and get_() methods which are just empty methods in the base class. At runtime the derived class virtual methods are linked and variables are written or read using set and get methods after a type or instance override.

Mirrors in UVM RAL !!!

RAL mirrors are shadow location of the DUT registers that are updated when RAL read or write methods are accessed from the test bench  , RAL mirror give the user test bench access to the register values for synchronizing test bench events without reading the DUT register. If the DUT internally modifies the content of any field or register through its normal operations (e.g., by setting a status bit or incrementing an accounting counter), the mirrored value becomes outdated. Memory are not mirrored in UVM RAL.RAL mirror value can be set using mirror() method , Mirror value can be updated to the DUT using update() method. At any point of time mirror value can be got using the get() method. set() method can be used to set the mirror value to DUT , the value actually written only when update() method is called.

Creating directed scenario in UVM !!!

Recommended  method  for closing coverage is to have test to run with multiple seeds , but many times certain scenarios can never be covered by the randomness and we require a directed test case. The way to write a directed test in UVM  is as follows.

• Disable the regular sequence from executing on the sequencer by setting count as 0 in the directed test case.

               set_config_int("*.sequencer", "count", 0);

• randomize the sequence in the directed way and execute the sequence on the sequencer using execute_item() method.

                 success = item.randomize();

               *.sequencer.execute_item(item);

TLM 2.0 Sockets in UVM !!!

Normally the connection between two processes is through port and export , but with TLM 2.0 we have sockets which provide asynchronous pipelined bi directional connectivity between components. Socket has both a export and port packaged together. A socket can  be initiator socket or target socket. Data flows in the forward direction from the initiator socket to target socket , there is also a backward path between Target socket to initiator socket. TLM connectivity between components can be easily encapsulated using sockets.

Phases in UVM !!!

UVM component have different phases like build() , connect() , end_of_elaboration() , start_of_simulation(), run() , extract() , check() & report().  Except run() all other phases are virtual functions , run() phase is a virtual task.

phases operate in a particular sequence  as follows build ->  connect  -->  end_of_elaboration --> start_of_simulation --> run --> extract --> check --> report. All the phases except build() phase is bottom up , build phase is top down. In UVM we have provision to add custom phase.

TLM process communication using TLM FIFO !!!

With normal TLM ports put will result in the consumers ability to process the transaction right away , TLM FIFO component in UVM is used to buffer transactions so that producer and consumer are independent of each other. TLM FIFO has methods like put() , get() and peek() to access transaction from the TLM FIFO. peek() method gets the transaction without removing transaction from the TLM FIFO. Some of the applications of TLM FIFO is buffering transactions for score boarding. 

Build in command line options in UVM !!!

here are some of the useful build in command line options in UVM.

instance specific factory override  :   +uvm_set_inst_override

type specific factory override          :   +uvm_set_type_override

integer configuration                        :   +uvm_set_config_int

string configuration                           :   +uvm_set_config_string

Timeout                                               :   +UVM_TIMEOUT

Max quit count                                   :   +UVM_MAX_QUIT_COUNT

Objection trace                                  :   +UVM_OBJECTION_TRACE

These command line options helps in quick debug and test writing. 

Sequence library in UVM !!!

Sequences can be grouped using  uvm sequence library ,  sequences can be registered to sequence library using the macro `uvm_add_to_seq_lib(). When the sequence library is started it randomly selects and executes the sequence depending on the selection mode. Selection modes can be any of the following

UVM_SEQ_LIB_RAND      --  Random selection of sequence 

UVM_SEQ_LIB_RANDC   --  Random selection without repeating the sequences

UVM_SEQ_LIB_ITEM       --  Execute  a single sequence item

UVM_SEQ_LIB_USER      --  user selects  sequences using select_sequence() method

Selection mode of the sequence library is set using  uvm_config_db().

sequence library can be used to create system level scenario using random sequences.

Interrupt handling using grab() and ungrab() sequencer in UVM !!!

One of the basic functionality on the processor interface of a verification environment is to service interrupts along with register read / write operations. Servicing the interrupt requires  stoping the ongoing register access sequence and executing the ISR sequence . This can be achieved  using grab()  method on the sequencer on an interrupt to stop the register read/write sequence and execute the interrupt sequence. ungrab() method should be used to return the sequencer control back to the register read/write sequence.

Generic Payload in UVM !!!

Generic payload is the default transport vehicle for TLM2  blocking and non blocking transport interface. Generic payload is a transaction class derived from uvm_sequence_item which enables it to be generated in sequences and transported to drivers through sequencers. Generic payload can be used for any memory mapped bus based system. Generic payload has property like m_address , m_command, m_byte_enables etc. Generic payload class has access methods for each of the property which is virtual enabling it to be used in the class that extends generic payload class.

It would be good idea to explore the generic payload transaction class before writing your own transaction class for memory mapped bus interface.

Base class library specific to product on top of RVM/VMM/OVM/UVM !!!

RVM/VMM/OVM/UVM provides rich set of features that can be used to develop a sophisticated test bench. Extending your Driven/monitor/scoreboard/sequence directly from the methodology may not be an ideal solution with respect to product specific requirement. The ideal way is have a set of base class extending from the methodology class which adds specific requirement which will be product line specific. Having company/product specific base class helps in better reuse and isolates the users from the changes introduced  due to new releases in the methodology. When ever specific base class is changed it can be qualified with the supported version of tool,methodology and VIP. This approach also helps to incrementally move towards the latest releases of the methodology ensuring current development effort is not stalled.

Layering sequences in UVM !!!

We come across different types of layering requirement for different  protocols. Basic ones are as follows.

1. One to one mapping  --  One higher level protocol frame is mapped to the payload of one lower level protocol frame.
2. One to many mapping -- One higher level protocol frame is mapped to the payload of many lower level protocol frames.
3. Many to one mapping  -- Many higher  level protocol frames are mapped to the payload of single lower level protocol frame.
4. Many to many mapping  -- Many higher level protocol frames are mapped to the payload of many lower level protocol frames. 

What ever be the layering scenario , the basic principle to generate a layering transaction is to randomize the higher level sequence and use byte_pack to convert it to a byte stream and package the bytes in the lower level sequence.

System verilog 2012 features !!!

I recently came across a paper presented at DVcon 2012 which summarized the proposed features of system verilog 2012 standard. The feature that  first grabbed my attention was multiple inheritance  support in system verilog similar to Java. This feature will ease the test bench development effort in future. The current methodology based on system verilog will potentially leverage this feature when it is available. Other feature which is also a good addition is the soft constraints which allow the constraints to be overridden without creating a conflict , currently we have to turn of the conflicting constraints using constraint mode to override a constraint. another interesting addition is the unique constraint to generate unique values across a list of variable or array elements , currently most of the users use custom logic or algorithm to generate unique values.

Callback in UVM !!!

Callbacks are empty virtual methods that are embedded in the user components at strategic  points to allow the user to make customization which allows better reuse.

In UVM this can be achieved in two ways. 

1. Simply add  empty virtual methods in the component  say in a driver  and invoke the virtual methods at appropriate locations , test writer or  the user extends the driver class implements the virtual methods and uses  set instance override to accomplish the functionality.
2. Create a class which extends form uvm_callback class and it  implements the virtual methods.  Use `uvm_do_callbacks() to place the virtual methods at strategic points in the component say a driver. Now the test writer or user extends the callback class and implements the virtual methods and registers or associate the extended callback class with the instance of the component say the driver using add to accomplish the functionality.

Adding user defined phase using uvm_phase !!!

In addition to the predefined phases available in uvm , the user has the option to add his own phase to a component. This is typically done by extending the uvm_phase class the constructor needs to call super.new which has three arguments 

1. name of the phase task or function
2. top down or bottom up phase
3. task or function

The call_task  or call_func and get_type_name need to be implemented to complete the addition of new phase.

Example

class custom_phase extends uvm_phase;

   function new();

      super.new(“custom”,1,1);

   endfunction

   task call_task  ( uvm_component parent);

    

     my_comp_type comp;

      

     if ( $cast(comp,parent) )

             comp.custom_phase();

    

   endtask

   virtual function string get_type_name();

      return “custom”;

   endfunction

endclass

Usage of uvm_resource_db & uvm_config_db !!!

Both uvm_config_db and uvm_resource_db share the same underlying database to store and retrieve information. Infact you can write a value to the database using uvm_config_db ::set() method and retrieve the information using uvm_resource_db::read_by_name().  The recommended method is to use uvm_config_db when hierarchical   based access is required.  When you want to share object and access it from different location without using the hierarchy you can use uvm_resource_db.

You can set a resource to the resource db using the uvm_resource_db::set()  method

Example

uvm_resource_db# (int）::set("enable","*",1,this);

To retrieve the information from the resource db you can use uvm_resource_db::read_by_name() method

Example

   Bit success;

   Success=uvm_resource_db#（int)::read_by_name("enable",get_full_name(),value,this);

   If(success==1’b0)
      `uvm_error("ERROR","cannot locate the resource ");

Accessing components bottom up using set_config_* and get_config_* in UVM !!!

One of the requirements in verification is to access variable bottom up  in the hierarchy this can be done in UVM using set_config_*  and get_config_*methods. In bottom up access you need to use hierarchical reference like  uvm_test_top.set_config_*  or  uvm_test_top.get_config_*  from the component in the lower level hierarchy to access component in top level hierarchy.  Top down access does not require the hierarchical reference to uvm_test_top , set_config_* and get_config_* can be used directly.