Gate level simulation !!!

One of time-consuming task in functional verification life cycle is gate level simulation. Gate level simulation can be broadly broken down into

1) Gate level simulation after synthesis to check equivalence with the RTL.

2) Gate level simulation with SDF on the post routed netlist.

A common question that is asked by many fokes is why step 2 is required. The netlist before P & R is compared with the netlist after P & R using formal tools for logic equivalence. Timing after P & R is checked with STA for all possible corners and configuration. It looks like an SDF simulation on post routed netlist is redundant.

Assume now a designer by mistake has place timing exception like false path and multi cycle path, the above condition goes undetected in the STA. Dynamic functional gate level simulation with SDF on post routed netlist is counter check for STA and catches if the designer has made mistakes on placing an timing exception.