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UVM sequences generally do not have access to the TLM ports In that case the TLM ports and other features available in the sequencer can be accessed from the sequence using p_sequencer reference. This feature is very useful in a layering scenario when higher level sequence is layered into the lower level sequence.
A blog to share my knowledge in ASIC design verification with respect to verification environment architecture, verification methodology, verification languages, protocols & EDA tool evaluations.
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The content on this blog and views expressed in the blog is my own and not related in any way to any of the organizations i worked for or working currently. I don't make any claims, promises or guarantees about the accuracy, completeness, or adequacy of the contents of this blog.