System verilog !!!

System verilog is now being used widely across the industry for any new code development. With the introduction of standard verification methodology like VMM from Synopsys, AVM from mentor, URM from cadence and OVM from cadence and mentor. There is a wide range of verification methodologies to choose from. Companies now are thinking in terms of verification reuse .All the verification methodology tell us how to write a reusable code ,but the real bottle neck is the legacy code written during time where no standard verification methodology like RVM,OVM & VMM existed. The solution to this issue is to re-write the code in more reusable way.

To use system verilog for the newer development in an SOC is also challenging. Luckily in some simulators have an interop mode where we can access HVL code from system verilog and vice versa. This solves the issue of integrating and using the legacy HVL code with system verilog. interop solves integration issues with system verilog but we still have to use two languages ( one for doing enhancements in legacy HVL code and system verilog for new development ). The Solution to this issue is to migrate the VERA/NTB code to system verilog. Most of the features used in VERA/NTB is available in system verilog. Syntax migration from one language to other is the fastest way to port your code and it takes only fraction of your development time. Industry standard conversion tools are available to covert your VERA/NTB code to System verilog or you can develop your own Perl script for migration. Open source perl scripts are also available on the internet to convert code from VERA/NTB to system verilog.