Sunday, August 9, 2009

six reasons why you should use system verilog for verification !!!

1) System verilog is an IEEE standard supported by multiple vendors, your code is portable across simulators.You are not tied to a single vendor, which is the case if you are using HVL like VERA/NTB/SPECMAN.

2) Free open source standard verification methodologys like VMM & OVM are available which can be used with system verilog.

3) Simulation speed will improve,if you are an HVL user using VERA/SPECMAN for verification.

4) Most of the VIP vendors support system verilog, building verification environment for SOC will not be an issue.

5) System verilog interoperability layers are available, you can re-use you VERA/NTB code from system verilog,similar arrangement is available for specman user too.

6) System verilog supports most of the constructs supported by HVL ( VERA/NTB/SPECMAN) , migration to sytem verilog for HVL users will not be an issue.