Wednesday, March 17, 2010

Another verification methodology UVM !!!

Recently through one of my friends i came to know about the development of a new verification methodology UVM.The UVM ( Universal verification methodology ) is being standardized by Accellera Technical Subcommittee (TSC) and claims to solve the system verilog cross methodology interoperability problem. This methodology is being suppored by all the 3 major EDA vendors synopsys, cadence and mentor. The advantage of switching to this methodology (when it is available) is portability of the methodology across different vendors. The base code for this methodology will be from OVM version 2.0.3.The base classes for UVM methodology is expected by Q1 2010.


It is still not clear about the backward compatability of this methodology with OVM. To me backward compatibility with VMM is out of question as the base code for this methodology is from OVM.

2 comments:

Tom said...

Those of us involved in the OVM are working hard to ensure that Accellera does not *not* create a third methodology, but rather standardizes the OVM as the UVM. This provides backwards compability for OVM usrs as well as a standard interoperability link (also defined by Accellera) between the UVM and VMM useers.

saravanan said...

If UVM is going to be third new methodology without any resemblence with OVM or VMM, It will be not be beneficial for either OVM or VMM user to migrate to UVM. Having backward comptibility with any one of the methodology in this case OVM will defenitly be beneficial. As an VMM/RVM user I definitly want to see some of the VMM features being added to this methdology but always open to other better ways of solving verification problems. It would be interesting to see the views of other VMM/RVM users.