Wednesday, April 14, 2010

System verilog 2009 new features !!!

Following are some of the new features of system verilog 2009 standard that caught my attention.

1)`begin_keyword `end_keyword

The above defines can be used between any section of code to maintain backward compatibility with verilog or system verilog 2005, very useful if you are migrating your testbench or design to system verilog, you might come across system verilog keywords used in your verilog design which can cause compile to fail. With system verilog 2009 just wrap the code with `begin_keyword and `end_keyword to get past the error without modifying your code.

2) Let construct substitute to macros ?

Package example_package;
Let expand_operation (a,b) = assert ( !a & b)
end package;

module test ( …);
import example_package::*;

always @ ( …) begin
expand_operation (read,write); // expands to assert(!read & write)

end module

3) Pure constraints

virtual class example;
pure constraint valid;

Allows you to declare pure constraint in the abstract class,just the declaration alone without implementation. The implementation of this constraint is provided in the extended class with the same constraint name.

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