Saturday, September 11, 2010
Interfacing CRV environment with procedural environments !!!
One of interesting challenges in verification is building constraint random verification environment on top of an existing code which is a procedural code.The challenges are unique to each of the environments; simplest solution is wrapping the procedural code in a transactor which is connected to a channel which interfaces with the constraint random generators. Transaction object attributes are mapped to different functionality in the procedural code.
Labels:
ASIC verification,
RVM/VMM,
system verilog,
VERA/NTB
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