Monday, January 3, 2011

Formal verification !!!

Recently i had a chance to know what formal verification is all about. My first impression on formal verification, it uses white box techniques to verify design against the black box approach used in constraint random verification. If your assertions or property definitions is accurate, formal tool can hit bugs faster than regular simulation effort. Ramp up on the formal tool takes little bit of time for people who are new to the formal verification world, debugging failures requires little bit of ramp up time as well. we need to debug failures without timing information by tracing schematics. When you get through the initial hiccups, you will definitely enjoy doing formal verification. Formal tool takes system Verilog or PSL assertions and tries to prove that your assertion can be violated by generating all possible stimuli.

2 comments:

Srivatsava said...

Mr. Saravanan.
I doing my grad studies at CSUS. I want to learn formal verification. I have knowledge of System Verilog (VMM) and good grip in SVA as well. What would be a good approach, where can I find th necessary material.

Thank you.

saravanan said...

Formal verification is more about getting hands on experience verifying design with the formal tools like 0-in from mentor graphics & IFV from cadence.Knowledge of SVA and PSL assertions will be very handy skill for formal verification. Try getting access to this tools through your university and experiment some projects of medium complexity with the formal tool. User manual of the tool will be a good starting point to know about formal verification.