Virtual sequences in UVM !!!

In a system level verification environment we require coordination of multiple components that run in parallel . Virtual sequence is used to have centralized control and coordinates stimulus generation across components. Virtual sequences executes on the virtual sequencer. Virtual sequencers have reference to other driver sequencers or other virtual sequencers. Virtual sequence can execute a transaction  items on other sequencers only.  By using virtual sequences you can reuse the sequence library of a component or a block level environment at system level.