Parameterized class in system verilog !!!

Verification component reuse is one of the basic requirement when building verification components.Parameterized class play a very important role in making a code generic. With parameterized class in system verilog data types , size of bit vectors can be declared generic in the class , different variations of the class can be created by varying the parameter value.

Example of a parameterized class

class data # ( type t=int , int size=8 )

      t                        a ;

      bit [ size-1 : 0] b ;

endclass

data # ( shortint , 16 )          halfword_data;

data # ( longint ,  32)                  word_data;